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MX9691L 1 p/n:pm0546 rev. 1.1, jul. 02, 1999 single chip solid state disk controller 1. feature host interface ? pcmcia 2.1 and pc card ata standard compatible. - memory mapped or i/o operation. ? compatible with all pc card services and socket service. ? fast ata host-to-buffer burst transfer rates up to 20mb/sec. which support pio mode 4(16.6mb/sec) and dma mode 2(16.6mb/sec). ? automatic sensing of pcmcia or true ide host inter face. ? integrated pcmcia attribute memory of 256 bytes (cis) - cis and buffer ram use same sram area to simplify internal bus design ? pcmcia card configuration register support. ? polarity control for host reset signal. ? pcmcia twin card support. ? pcmcia based ata address decode support. ? emulate the ibm task file for pc/at. ? separate status for host reset signal and host program reset. ? separate host and disk interrupt pins. flash memory interface ? support all the control signals to execute read/ write/ erase operation for flash memory. ? flexible disk capacity configuration for series type or linear type flash memory - upto 32mb(unformatted) capacity for 16 pcs. 16mbit linear type flash memory. - upto 1gb(unformatted) capacity for 32 pcs. 256mbit series type flash memory. ? flash memory power down or write protect control support. ? flash memory ready/busy status detect. ? inverted data bus control to reduce flash memory program/erase operation in dos fat and ecc code field. ? optional store firmware in flash memory array w/o external rom while mxic's mx29f1610(linear type) used. - allow code fetch in shadow rom during flash memory program or erase. buffer ram manager ? dual port circular buffer ram control ? 1kb data buffer ram. ? automatically correct error data in buffer ram. - single word error correct and double word detect. ? provide logic to speed up buffer ram access. ? support 8 bit as well as 16 bit transfer on host bus. dsp core ? high performance mx93011 dsp (21mips) core. ? 4kb internal ram(direct access). ? 2kb internal expansion ram(indirect access) for store data or shadow rom space. ? ice debugging mode supported to ease system verification. ? lower power and automatic power saving operation. - automatic standby mode. (operating current < 10ma, vcc=5.5v), wake-up by interrupt signal. - very low operating current sleep mode. (<1ma,vcc=5.5v), wake-up by host reset signal or host program reset or ata command asserted by host. technology ? 128 pin lqfp(14x14x1.4 mm 3 ) ? 128 pin tqfp(14x14x1.0 mm 3 ) ? 0.6um low-power, high-speed cmos technology. ? 5volt 10% or 3.3volt 5%. utility support ? provide integrated test environment with 82365sl- compatible adaptor. ? firmware upload from host and allows easy upgrade for custom feature. ? physical devices test cover basic pcb test after assembly and more detial analysis. ? logical sector test cover ssd functionality and data transfer test.
2 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 2. general description the macronix's solid state disk controller MX9691L is a wide-range supply voltage(3.3volt~5volt) and fully in- tegrated flash memory controller that provides all the control logic for pcmcia/true ide host and flash memory. the MX9691L combines 1kb dual-port buffer and buffer manager, integrated mx93011 dsp core, and a complete host interface for both the pc card ata and true ide standard. the MX9691L provides flexible disk capacity configu- ration and supports all the control signals to execute read/write/erase operation for linear type or series type flash memory chip. it is typically configured with up to 32mb(unformatted) capacity for 16 pcs. 16mbit linear flash memory or 1gb(unformatted) capacity for 32 pcs. 256mbit series type flash memory while capacity extention mode is enabled for series type flash memory used. the MX9691L also provides flexible architecture to implement defect management and wear-leveling by firmware for series type or linear type flash memory. in linear mode, the linear type 16 mbit flash memory is supported, such as mxic's mx29f1610 etc. in flash memory interface there are two banks of flash memory to be provided. each bank support 8 pcs. flash memory when linear type flash memory is used. in series mode, the se- ries type 16mbit/32mbit/64mbit/256mbit flash memory is supported, such as toshiba's tc5816ft/tr or tc58v32ft, samsung's km29n16000t/r or km29n32000ts/rs etc. each bank support or 16 pcs. flash memory when series type flash memory is used. the MX9691L is fully compliant with the pc card ata specification. it includes 256 bytes of integrated attribute memory(for the required card information structure) and four card configuration registers. the pcmcia device driver can access the MX9691L 's ata command block through four different modes by writing the different modes by writing the configuration index of the attribute memory configuration option register.
3 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 3. pin configuration 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 ha2 reg# ha1 spkr ha0 gndp stschg hd0 hd8 hd1 hd9 hd2 hd10 iois16# pwr_rst test vccp x1 x2 gndp romwr# romcs# sctrl# hlda# vccx32 swait# nc gndx32 dce# pce# wr# rd# fa16 fa15 a14 a13 a12 led# gndp a11 a10 a9 a8 fa19 fry/fby# int1# nmi# hold# vccp wrflash0# wrflash1# fa18 fa17 a15 a7 a6 gndp a5 a4 a3 a2 a1 a0 wp# d7 d6 d5 d4 d3 gndp d2 d1 d0 rdflash0# fce7# fce2# vccp fce1# fce0# gnd fce6# fce5# fce4# fce3# vcc rdflash1# d8 d9 d10 d11 gndp d12 d13 d14 d15 se# hd3 hd11 hd4 hd12 hd5 hd13 hd6 hd14 gndp ireq# inpack# hd7 hd15 hce1# hce2# ha10 vccp hoe# ior# ha9 gnd iow# ha8 vcc hwe# ha7 ha6 ha5 hreset ha4 wait ha3 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 MX9691L
4 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 4. pin description host interface symbol no. type description ha[10:0] 92,94, i host address line 10-0. 96-97,99 (cmos) these pins include internal pull-up resistors. 101-103, 106,109, 113 hd[15:0] 84-89, i/o host data line 15-0. 116-117, (ttl) these pins include internal bus holder circuit that keep 121-128 previous state when tri-state. hoe#,hwe# 104,111 i host memory read/write/mode select : (cmos) both pins include internal pull-up resistors that is default in pcmcia mode. ior#,iow# 107,110 i host i/o access. (cmos) both pins include internal pull-up resistor. hreset/hreset# 100 i the host reset signal, when active, initializes the control/ (cmos) status registers and stops any command in process. in pcmcia mode, the signal is active high. in true ide mode, this signal is active low. this signal include internal pull-down resistor. wait/ iochrdy 98 o,od wait or input channel ready : in both pcmcia and (cmos) true ide modes, this signal holds host transfers until the controller is ready to respond. rdy/bsy#/ 119 o, z ready/busy or host interrupt : in pcmcia mode, ireq#/ (cmos) this signal has two functions. in pcmcia common memory hostint mode, this signal is ready/busy. it is asserted busy by the reset logic, and can be deasserted by the dsp or represents the ready/busy bit of ata status register. in pcmcia i/o mode, this signal is ireq#. in true ide mode, this active high signal is hostint, which, when enable, send an interrupt to the host.
5 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 symbol no. type description wp/iocs16# 83 o,od write protect or 16-bit i/o transfer : (cmos) in pcmcia mode, this bit has two functions. in pcmcia common-memory mode,this signal indicates write protect. in pcmcia i/o mode, when iois16# is asserted low, it indicates that a 16-bit data transfer is active on pcmcia bus. in true ide mode, the iocs16# signal indicates that a 16-bit buffer transfer is active on the host bus. this open drain signal is only driven on assertion(low). reg#/dack# 95 i attribute memory and i/o select : (cmos) in pcmcia mode, this signal is used to select attribute memory and i/o space. in true ide mode, this signal is used during dma with the dreq, ior# and iow# signals to transfer data between the host and the MX9691L. this pin includes an internal pull-up resistor. hce1#/ 115 i card enable 1 or chip select 0:in pcmcia mode,this signal cs1fx# (cmos) is card enable 1. this signal can enable either even or odd numbered-address bytes onto hd7:0. in true ide mode, this signal accesses the mx9691 command block registers. this input is ignored during dma data transfer, i.e. when the dack# signal is low. this pin includes an internal pull-up resistor. hce2#/ 114 i card enable 2 or chip select 1: cs3fx# (cmos) in pcmcia mode,this signal is card enable 2. this signal can enable odd numbered-address bytes onto hd15:8. in true ide mode, this signal accesses the MX9691L control block registers. this pin includes an internal pull-up resistor. inpack#/ dreq 118 o input acknowledge or dma request :in pcmcia mode, this (cmos) signal is asserted when the mx9691 is configured to respond to i/o card read cycles at all addresses. in true ide mode, this signal is dreq and is issued during dma transfers to indicate that the MX9691L is ready for dma transfer. spkr/dasp# 93 i/o speaker or slave present : in pcmcia mode, the (cmos) output-enable for this signal is controlled by the card configuration registers. in true ide mode, this signal is used as the slave-present detector. stschg/ 90 i/o status change or pass diagnostics :in pcmcia mode, this pdiag# (cmos) signal is used to indicate changes in the rdy/bsy#,wp signals in card configuration registers. in true ide mode, this active low signal is used between two embedded ata drive to indicate that the drive in slave mode has passed diagnostics.
6 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 external memory bus interface symbol no. type description d[15:0] 33-37,39-41, i/o dsp io/ram/rom/flash memory array external data bus. 55-58,60-63 (cmos) these pins include internal pull- up resistors. a[15:0] 3-5,8-11, i/o in free-run mode, these signals are output that used as dsp 22-24,26-31 (cmos) io/ram/rom external address. a14-a0 are used for flash memory array address also. in upgrade mode, these address are used for rom address that controlled by cyh,cyl registers. in ice-debugging mode,these address are input, asserted by dsp ice(external mx93011 dsp). and the internal dsp is disabled at this time. these pins include internal pull-up resistors. pce# 67 i/o in free-run mode, this signal is output that is used as (ttl) external program chip enable. in upgrade mode, this signal is drived to high. in ice-debugging mode, this signal is input, asserted by dsp ice(external mx93011 dsp). and the internal dsp is disabled at this time. this pin includes a bus holder circuit. dce# 68 i/o in free-run mode, this signal is output that is used as (ttl) external data chip enable. in upgrade mode, this signal is drived to high. in ice-debugging mode, this signal is input, asserted by dsp ice(external mx93011 dsp). and the internal dsp is disabled at this time. this pin includes a bus holder circuit. rd# 65 i/o in free-run mode, this signal is output that is used as dsp (ttl) io/ram/rom external read. in upgrade mode, this signal is output and asserted when the data register is read in host interface. in ice-debugging mode, this signal is input, as serted by dsp ice(external mx93011 dsp). and the internal dsp is disabled at this time. this pin includes a bus holder circuit. wr# 66 i/o in free-run mode, this signal is output that is used as dsp (ttl) io/ram/rom external write. in upgrade mode, this signal is drived to high. in ice-debugging mode, this signal is input, asserted by dsp ice(external mx93011 dsp). and the internal dsp is disabled at this time. this pin includes a bus holder circuit. nmi# 15 i non maskable interrupt pin. (cmos) this pin includes an pull-up resistor. int1# 14 i/o in free-run mode, this signal is input that is used as (cmos) interrupt pin. interrupt will be internally asserted also when data transfer done, or command end. in ice-debugging mode, this signal is output and asserted when data transfer done, or command end. this pin includes an pull-up resistor.
7 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 symbol no. type description hold# 16 i/o in free-run mode, this signal is input that is used as holding (cmos) dsp clock down and release bus. bus hold will be internally asserted also when upgrade mode enable. in ice-debug ging mode, this signal is output and asserted when upgrade mode enable. this pin includes an pull-up resistor. hlda# 73 i/o in free-run mode, this signal is output that is used as ack to (cmos) hold# signal. this signal will be internally sent to pcmcia/ ata interface also when upgrade mode enable. in ice-de bugging mode, this signal is input and ack to hold# when upgrade mode enable. xf#/sctrl# 74 o sleep control, this pin can be directly asserted to low while (cmos) power down bit is set by dsp. this pin is connected to external rc circuit. default inactive (logic high). in ice-debugging mode, this signal is used to reset dsp. flash memory interface symbol no. type description fa19/cle 12 o in linear mode, this signal is used as flash memory chip high (cmos) address line 19. in series mode, this signal is used as flash memory chip command latch enable. fa18/ale/ 20 i/o in linear mode, this signal is used as flash memory chip high icemode (cmos) address line 18. in series mode, this signal is used as flash memory chip address latch enable. this signal is also used to select whether the mx9691 initializes in free-run mode or in ice-debugging mode at power-on reset. if this pin go high, then the MX9691L will switch to free-run mode at power-on reset,and if this pin remains low, then the MX9691L will initializes in ice-debugging mode. this pin includes an internal pull-up resistor. ice-debugging mode select : icemode=1 > f ree-run mode. icemode=0 > ice-deb ugging mode. fa17/erom 21 i/o(cmos) this signal is used as flash memory chip high address line 17. this signal is also used to select whether the firmware store in linear type flash memory array or in separate external rom at power-on reset. if this pin go high, then the firmware will be executed in linear type flash memory array, and if this pin remains low, then the firmware will be executed in separate external rom. store firmware in external rom or linear type flash memory array select: erom = 0 > store in exter nal rom. erom = 1 > store in flash memory array. this pin includes an internal pull-up resistor.
8 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 symbol no. type description fa[16:15]/ 1-2 i/o this signal is used as flash memory chip high address line atadet[1:0] (cmos) 16-15. these signals are also used to select configuration in true ide mode at power-on reset. atadet1 is connected to dsp's ipt1. atadet0 is connected to dsp's ipt0. vdd is connected to ipt2. master/slave selection in true ide mode : atadet1 atadet0 mode selected 1 1 one drive 0 0 master of two drives 1 0 slave of two drives this power-on configuration can be accessed from pcmcia/ ata port 601ch bit3-2. these pins include internal pull-up resistors. rdflash1# 54 o flash memory ouptut enable 1 for bank1: (cmos) this signal will be asserted by flash memory read operation when flash memory read address latch, port 601dh bit 8= 1(i.e. fa23=1). note: flash memory access window is mapped to 32kw data and code space 8000h~ffffh. rdflash0# 42 o flash memory ouptut enable 0 for bank0: (cmos) this signal will be asserted by flash memory read operation when flash memory read address latch, port 601dh bit 8 = 0(i.e. fa23=0). wrflash1# 19 o flash memory write enable 1 for bank1: (cmos) this signal will be asserted by flash memory write operation when flash memory write address latch, port 601fh bit 8 = 1(i.e. fa23=1). wrflash0# 18 o flash memory write enable 0 for bank0: (cmos) this signal will be asserted by flash memory write operation when flash memory write address latch, port 601fh bit 8 = 0(i.e. fa23=0).
9 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 symbol no. type description fce[7:0]# 43-44, o flash memory chip enable 7-0 : 46-47 (cmos) in linear mode, these signals are decoded from port 601dh 49-52 bit 7-5 when flash memory read or port 601fh bit 7-5 when flash memory write. decoding combination : bit7 bit6 bit5 fce[7:0]# 0 0 0 11111110 0 0 1 11111011 0 1 0 11101111 0 1 1 10111111 1 0 0 11111101 1 0 1 11110111 1 1 0 11011111 1 1 1 01111111 in series mode, these are decoded from port 601dh bit 7-5 only when port 601eh bit 2 is set. pwd0#/wp# 32 o in linear mode, this signal is used as deep power-down (cmos) control of flash memory chips of bank0. pwd0# is active low and also locks out erase or program operation providing data protection during power transitions. power down pin pwd0# will be active if fa23=1. in series mode, this signal is used to protect the device from inadvertent programming or erasing. wp# is active low. pwd1#/se# 64 o in linear mode, this signal is used as deep power-down (cmos) control of flash memory chips of bank1. pwd1# is active low and also locks out erase or program operation providing data protection during power transitions. power down pin pwd0# will be active if fa23=0. in series mode,this signal is used to spare area control. se# is active low. fry/fby# 13 i flash memory ready/busy input: (cmos) this signal indicate the state of erase or program operation in flash memory chips.this pin includes an internal pull-up resistor.
10 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 control rom interface symbol no. type description romcs#/ 75 o rom chip select/flash memory data buffer enable : fwin# (cmos) in free-run mode, this signal is used as rom chip enable if firmware that stored in external rom. in ice-debugging mode, this signal is used as flash memory data buffer (74640) enable if firmware that stored in flash memory array. romwr#/fdir 76 o rom write enable/flash memory data buffer direction (cmos) control: in free-run mode, this signal is used as rom write enable if firmware that stored in external rom. in ice-debugging mode, this signal is used as flash memory data buffer (74640) direction control if firmware that stored in flash memory array. miscellaneous symbol no. type description x1 79 i crystal input. x2 78 o crystal ouput. swait# 71 i(cmos sleep wait, this pin is connected to external rc circuit. schmitt) n.c. 70 o no connect. test 81 i this signal is used to select the main system clock, either (cmos) from external clock source if this signal is high or from internal pll circuit if this signal is low. this pin includes an internal pull-up resistor. pwr_rst# 82 i(cmos power on reset, cmos schmite-triggered: schmitt) the MX9691L include debouncing circuit to stabilize internal dsp reset signal. led# 6 o led output: (cmos) this signal is connected to external led in debugging system to indicate system status. the led will be turn-on during reset. the contorl firmware will turn off the led after h/w initialization and pass diagnostics. if system fail, the control firmware will flash the led to indicate some error occur. this signal will be high if port 601ch bit0 set to 1 or optr bit2 set to 1. vcc 17,45,53, 5 or 3.3 volt power pin 72,80,105, 112 gnd 7,25,38, ground pin 48,59,69, 77,91,108, 120
11 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 5. functional and operation description 5-1. block diagram mx93011 dsp core clock & reset register bank 1kb buffer ram 4kb internal ram 2kb internal ram flash memory control ecc control logic 256 byte cis ram MX9691L signal chip solid state disk controller buffer ram control external memory bus clock host interface pcmcia/ata flash interface pcmcia/ata interface
12 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 5-2. system memory map data space : address function & usage 0000h~007fh internal ram (128w) to store control variables 0080h~07ffh internal ram(1920w) for flash memory algorithm usage 0800h~5fffh user define (22kw) 6000h~63ffh i/o range(1kw): ata ctl. use i/o range (6000h~601fh) 6400h~6fffh user define (3kw) 7000h~73ffh user define (1kw) 7400h~77ffh internal ram (1kw) for expansion ram or shadow rom space 7800h~7fffh rom data space(2kw) 8000h~ffffh flash memory access windows(32kw) program space : address function & usage 0000h~77ffh rom program space (32kw) 7800h~7fffh unused 8000h~ffffh flash memory access windows(32kw) 5-3. power-on detection * store firmware in external rom or flash memory array : fa17/erom = 0 > store in external rom fa17/erom = 1 > store in flash memory array * master/slave selection in true ide mode : fa16/atadet1 fa15/atadet0 mode selected 1 1 one drive 0 0 master of two drives 1 0 slave of two drives note : for some customers design the master/slave selection is selected by only one jumper that may be fa16 or fa15. it need to change firmware only. * ice debugging mode select : fa18/icemdoe = 0 ---> ice-debugging mode fa18/icemode = 1---> free-run mode, dsp fetch code from external memory bus and execute it. * flash memory data buffer control romcs# is replaced by fwin# if ice-debugging mode & firmware in linear type flash memory array. romwr# is replaced by fdir if ice-debugging mode & firmware in linear type flash memory array. * pcmcia mode or true ide mode select hoe# mode 0 true ide mode 1 pcmcia mode to enable true ide mode this input should be grounded by the host.
13 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 5-4. decoding configuration of all registers in host interface * common momory mode decode register address register read enable register write enable ce1# ce2# reg# ha10 ha9:4 ha3:0 hoe# =0 hwe# = 0 0 0 1 0 xh 000xb read data register hd[15:0] write data register hd[15:0] 0 1 1 0 xh 0000b read data hd[7:0] write data hd[7:0] even & odd byte even & odd byte 1 0 1 0 xh 0000b error status hd[15:8] features hd[15:8] 0 1 1 0 xh 0001b error status hd[7:0] features hd[7:0] 1 0 1 0 xh 0001b error status hd[15:8] features hd[15:8] 0 0 1 0 xh 001xb sector count hd[7:0] sector count hd[7:0] sector number hd[15:8] sector number hd[15:8] 0 1 1 0 xh 0010b sector count hd[7:0] sector count hd[7:0] 0 1 1 0 xh 0011b sector number hd[7:0] sector number hd[7:0] 1 0 1 0 xh 0011b sector number hd[15:8] sector number hd[15:8] 0 0 1 0 xh 010xb cyl. low hd[7:0] cyl. low hd[7:0] cly. high hd[15:8] cly. high hd[15:8] 0 1 1 0 xh 0100b cyl. low hd[7:0] cyl. low hd[7:0] 0 1 1 0 xh 0101b cly. high hd[7:0] cly. high hd[7:0] 1 0 1 0 xh 0101b cly. high hd[15:8] cly. high hd[15:8] 0 0 1 0 xh 011xb drive/head hd[7:0] drive/head hd[7:0] ctl. status hd[15:8] command hd[15:8] 0 1 1 0 xh 0110b drive/head hd[7:0] drive/head hd[7:0] 0 1 1 0 xh 0111b ctl. status hd[7:0] command hd[7:0] 1 0 1 0 xh 0111b ctl. status hd[15:8] command hd[15:8] 0 0 1 0 xh 100xb read data register hd[15:0] write data register hd[15:0] (duplicate) (duplicate) 0 1 1 0 xh 1000b read data hd[7:0] write data hd[7:0] even & odd byte (duplicate) even & odd byte (duplicate) 1 0 1 0 xh 1001b read data hd[15:8] write data hd[15:8] odd byte (duplicate) odd byte (duplicate) 0 1 1 0 xh 1001b read data hd[7:0] write data hd[7:0] odd byte (duplicate) odd byte (duplicate) 0 0 1 0 xh 110xb undefined hd[7:0] undefined hd[7:0] error status hd[15:8] features hd[15:8] (duplicate) (duplicate) 0 1 1 0 xh 1101b error status hd[7:0] features hd[7:0] (duplicate) (duplicate) 0 0 1 0 xh 111xb alternate ctl. status hd[7:0] device ctl. hd[7:0] drive/head hd[15:8] undefined hd[15:8] 0 1 1 0 xh 1110b alternate ctl. status hd[7:0] device ctl. hd[7:0]
14 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 * independent i/o mode decode register address register read enable register write enable ce1# ce2# reg# ha9:4 ha3:0 ior# =0 iow# = 0 0 0 0 xh 0000b read data register hd[15:0] write data register hd[15:0] 0 1 0 xh 0000b read data hd[7:0] write data hd[7:0] even & odd byte even & odd byte 1 0 0 xh 0000b error status hd[15:8] features hd[15:8] 0 1 0 xh 0001b error status hd[7:0] features hd[7:0] 1 0 0 xh 0001b error status hd[15:8] features hd[15:8] 0 1 0 xh 0010b sector count hd[7:0] sector count hd[7:0] 0 1 0 xh 0011b sector number hd[7:0] sector number hd[7:0] 1 0 0 xh 0011b sector number hd[15:8] sector number hd[15:8] 0 1 0 xh 0100b cyl. low hd[7:0] cyl. low hd[7:0] 0 1 0 xh 0101b cly. high hd[7:0] cly. high hd[7:0] 1 0 0 xh 0101b cly. high hd[15:8] cly. high hd[15:8] 0 1 0 xh 0110b drive/head hd[7:0] drive/head hd[7:0] 0 1 0 xh 0111b ctl. status hd[7:0] command hd[7:0] 1 0 0 xh 0111b ctl. status hd[15:8] command hd[15:8] 0 0 0 xh 1000b read data register write data register hd[15:0](duplicate) hd[15:0](duplicate) 0 1 0 xh 1000b read data hd[7:0] write data hd[7:0] even & odd byte (duplicate) even & odd byte (duplicate) 1 0 0 xh 1001b read data hd[15:8] write data hd[15:8] odd byte (duplicate) odd byte (duplicate) 0 1 0 xh 1001b read data hd[7:0] write data hd[7:0] odd byte (duplicate) odd byte (duplicate) 0 1 0 xh 1101b error status hd[7:0](duplicate) features hd[7:0](duplicate) 0 1 0 xh 1110b alternate ctl. status hd[7:0] device ctl. hd[7:0] 0 1 0 xh 1111b drive/head hd[7:0] not used 1 0 0 xh 1111b drive/head hd[15:8] not used register address register read enable register write enable 0 1 1 0 xh 1111b drive/head hd[7:0] not used 1 0 1 0 xh 1111b drive/head hd[15:8] not used 0 0 1 1 xh xxxxb read data register hd[15:0] write data register hd[15:0] 0 1 1 1 xh xxx0b read data hd[7:0] write data hd[7:0] even & odd byte even & odd byte 0 1 1 1 xh xxx1b read data hd[7:0]odd byte write data hd[7:0]odd byte 1 0 1 1 xh xxx0b read data hd[15:8] odd byte write data hd[15:8] odd byte 1 0 1 1 xh xxx1b read data hd[15:8] odd byte write data hd[15:8] odd byte
15 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 * primary ata mode decode register address register read enable register write enable ce1# ce2# reg# ha9:0 ior# =0 iow# = 0 0 0 0 1f0h read data register hd[15:0] write data register hd[15:0] 0 1 0 1f0h read data hd[7:0]even & odd byte write data hd[7:0]even & odd byte 1 0 0 1f0h error status hd[15:8] features hd[15:8] 0 1 0 1f1h error status hd[7:0] features hd[7:0] 1 0 0 1f1h error status hd[15:8] features hd[15:8] 0 1 0 1f2h sector count hd[7:0] sector count hd[7:0] 0 1 0 1f3h sector number hd[7:0] sector number hd[7:0] 1 0 0 1f3h sector number hd[15:8] sector number hd[15:8] 0 1 0 1f4h cyl. low hd[7:0] cyl. low hd[7:0] 0 1 0 1f5h cly. high hd[7:0] cly. high hd[7:0] 1 0 0 1f5h cly. high hd[15:8] cly. high hd[15:8] 0 1 0 1f6h drive/head hd[7:0] drive/head hd[7:0] 0 1 0 1f7h ctl. status hd[7:0] command hd[7:0] 1 0 0 1f7h ctl. status hd[15:8] command hd[15:8] 0 1 0 3f6h alternate ctl. status hd[7:0] device ctl. hd[7:0] 0 1 0 3f7h drive/head hd[7:0] not used 1 0 0 3f7h drive/head hd[15:8] not used * secondary ata mode decode register address register read enable register write enable ce1# ce2# reg# ha9:0 ior# =0 iow# = 0 0 0 0 170h read data register hd[15:0] write data register hd[15:0] 0 1 0 170h read data hd[7:0]even & odd byte write data hd[7:0]even & odd byte 1 0 0 170h error status hd[15:8] features hd[15:8] 0 1 0 171h error status hd[7:0] features hd[7:0] 1 0 0 171h error status hd[15:8] features hd[15:8] 0 1 0 172h sector count hd[7:0] sector count hd[7:0] 0 1 0 173h sector number hd[7:0] sector number hd[7:0] 1 0 0 173h sector number hd[15:8] sector number hd[15:8] 0 1 0 174h cyl. low hd[7:0] cyl. low hd[7:0] 0 1 0 175h cly. high hd[7:0] cly. high hd[7:0] 1 0 0 175h cly. high hd[15:8] cly. high hd[15:8] 0 1 0 176h drive/head hd[7:0] drive/head hd[7:0] 0 1 0 177h ctl. status hd[7:0] command hd[7:0] 1 0 0 177h ctl. status hd[15:8] command hd[15:8] 0 1 0 376h alternate ctl. status hd[7:0] device ctl. hd[7:0] 0 1 0 377h drive/head hd[7:0] not used 1 0 0 377h drive/head hd[15:8] not used
16 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 5-5. automatic power saving mode there are four power saving modes defined in solid state disk(ssd) system. these four power saving modes are executed by firmware which use dsp's soft-hold and power down function and addition logic circuit to imple- ment it. active mode : in active mode the ssd is capable of execution to file read and write operation. idle mode : in idle mode the ssd polls the events that include command_in or time_out events. if read/write command is asserted then the ssd will enter the active mode. standby mode : the ssd will enter the standby mode after time_out(1.25ms) event occurs or standby com- mand is asserted. the ssd controller MX9691L will en- ter soft_hold condition. the mx9619 will stop program execution and shut off most circuit activities to save many power comsumption. the MX9691L will automatically wake up and enter the active mode if any command is asserted. sleep mode : the ssd will enter the sleep mode after sleep command is asserted. this is most power saving mode. the ssd controller MX9691L will enter soft _hold condition and stop main clock and then the all system activities will stop. this mode can be waked up by h/w reset, s/w reset or ata command asserted. the h/w re- set will reset all h/w circuits and the host must reconfigure the ssd before any command is assseted. the s/w re- set will set the busy status until the ssd is ready for ac- cepting command, the host don't need any h/w reinitialization. the duration of h/w and s/w reset must keep enough for main clock stabilization. the ata command asserted to wake-up latency need the external rc circuit delay for clock stabilization while the solid state disk(ssd) had entered sleep mode. power saving flow power_up reset initialize time-out1 or standby cmd standby idle s/w reset exit command in time-out2 or sleep cmd wake-up latency command_in command in sleep h/w reset active
17 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 5-6. registers definition * registers list type of register location pcmcia/ata interface 6000h, 6001h, 6002h, 6003h, 6004h, 6005h, 6006h, 6007h, 600bh, 6010h, 6011h, 6012h, 6013h, 6019h, 601ah, 601bh, 601ch pc interrupt control 6009h, 600ah buffer manager and dma 6008h, 6014h, 6015h, 6016h, 6017h, 6018h ecc control 600ch, 600dh, 600eh, 600fh flash memory interface 601dh, 601eh, 601fh * register description port 6000h : bit function description at control/status register default reset value : 01h 7 r/w: drive ready (drive 0) 6 r/w: drive seek complete (drive 0) 5 r/w: corrected data 4 r: ata int. enable 3 r: at software reset 2 r/w: host interrupt 1 r/w: error bit 0 r/w: busy bit port 6001h : bit function description default reset value : 00h 7:0 r/w: error register (map to command block 1f1h) port 6002h : bit function description default reset value : 01h 7:0 r/w: sector count register (map to command block 1f2h) port 6003h : bit function description default reset value : 01h 7:0 r/w: sector number register (map to command block 1f3h)
18 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 port 6004h : bit function description default reset value : 00h 7:0 r/w: cyclinder low register (map to command block 1f4h) port 6005h : bit function description default reset value : 00h 7:0 r/w: cyclinder high register (map to command block 1f5h) port 6006h : bit function description default reset value : a0h 7:0 r/w: drive/head register (map to command block 1f6h) port 6007h : bit function description default reset value : 00h 7:0 r: command register (map to command block 1f7h) port 6008h : bit function description buffer ram size control register default reset value : 40h 7 r/w: test mode 1 for hap/dap test 0 : disable 1 : enable 6 r/w: bit write gate state of drive 0 : enable 1 : disable 5 r: pcmcia or true ide mode 0 : true ide mode 1 : pcmcia mode 4 r/w: auto dap increment 0 : disable 1 : enable 3 r/w: shadow rom control 0 : disable 1 : enable 2:0 r/w: buffer ram size control 00x : 32kw 010 : 16kw 011 : 8kw 100 : 4kw 101 : 2kw 110 : 1kw
19 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 111 : 512w port 6009h : bit function description host interrupt status default reset value : 00h 7 r: power-down timer time-out detected 6 r: card configuration register write detected 5 r: cis accessed detected 4 r: hreset detected 3 r: pc srst(or pcmcia srst) detected 2 r: pc status read detected 1 r: pc selection 0 r: pc transfer done port 600ah : bit function description host interrupt enable default reset value : 00h 7 r/w: power-down timer time-out detected enable. 6 r/w: card configuration register write detected enable 5 r/w: cis accessed detected enable 4 r/w: hreset detected enable 3 r/w: pc srst(pcmcia srst) detected enable 2 r/w: pc status read detected enable 1 r/w: pc selection enable 0 r/w: pc transfer done enable port 600bh : bit function description default reset value : 00h 7:0 r: feature register (map to command block 1f1h)
20 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 port 600ch : bit function description ecc control register default reset value : 00h 7 r/w: ecc function suspend 0 : normal 1 : suspend 6 r/w: correction speed select 0 : full speed (max. clock frequency) 1 : half speed (1/2 max. clock frequency) 5 r/w: encode/decode function selection 0 : encode 1 : decode 4 r/w: reset ecc circuit 0 : reset 1 : normal 3 r: uncorrectable error flag 2 r: correctable error flag 1 r: correction done flag 0 r/w: start ecc correct function enable/disable 0 : disable 1 : enable port 600dh : bit function description default reset value : 0000h 15:0 r/w : ecc 0 register port 600eh : bit function description default reset value : 0000h 15:0 r/w : ecc 1 register port 600fh : bit function description default reset value : 0000h 15:0 r/w : ecc 2 register port 6010h : bit function description default reset value : 00h
21 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 7:0 r: configuration option register (map to attribute memory 200h) port 6011h : bit function description default reset value : 00h 7:0 r: card configuration and status register (map to attribute memory 202h) port 6012h : bit function description default reset value : 0ch 7:0 r: pin replacement register (map to attribute memory 204h) port 6013h : bit function description default reset value : 00h 7:0 r: socket and copy register (map to attribute memory 206h) port 6014h : bit function description default reset value : 0000h 15:0 r/w : host address pointer port 6015h : bit function description default reset value : 00ffh 15:0 r/w : at stop pointer port 6016h : bit function description default reset value : 0000h 15:0 r/w : disk address pointer port 6017h : bit function description dma control register default reset value : 08h 7 r/w: drive ready (drive 1) 6 r/w: drive seek complete (drive 1) 5 r/w: set bsy upon xfer done 0 : disable 1 : enable 4 r/w: enable auto interrupts - at only 0 : disable
22 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 1 : enable port6017h: bit function description 3 r/w: buffer ram chip enable 0 : enable 1 : disable 2 r/w: host bus direction 0 : start buffer ---> at bus 1 : start at bus ---> buffer when set 1 r: a completion of at dma xfer 0 r/w: start data transfer between at bus and buffer ram 0 : disable 1 : enable port 6018h : bit function description 15:0 r/w : access port into buffer ram port 6019h : bit function description pcmcia control register 7 r: true ide mode 6 r: common memory mode 5 r: i/o mode 4 r/w: host ready 3 r/w: no drive address 2 r/w: internal registers write pulse width 0 : 2 system clock 1 : 1 system clock 1 r/w: reserved.
23 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 0 r/w: reserved. port 601ah : bit function description auxi_ctl_1 reg. default reset value : 00h 7 r/w : dasp 6 r/w : host interrupt level mode or pulse mode select 0: level mode 1: pulse mode 5 r/w : pdiag 4 r/w : dasp output enable 3 r/w: write protect enable 0: disable 1: enable 2 r/w: pdiag output enable 1 r/w: master/slave mode enable 0: disable 1: enable 0 r/w: master/salve of true ide mode 0: master 1: slave port 601bh : bit function description auxi_ctl_2 reg. default reset value : 00h 7:4 reserved. 3 r/w: reserved. 2 r/w: deep power down control for automatic wake-up function from sleep mode. 0 : disable 1 : enable 1 r/w: reserved. 0 r/w: disk interrupt polarity 0: low active
24 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 1: high active port 601ch : bit function description auxi_ctl_3 reg. default reset value : 0000h 15 reserved. 14 r/w : test mode 2 for timer 0 : normal mode 1 : test mode enable 13 r : drq 12 r : time out status 1 : time out event occurence 11 r/w: timer enable/disable 0 : disable 1 : enable 10:9 r/w: pow er-down timer time-out select for 25mhz main clock 00 : 16 x 1.28 = 20.48 sec. 01 : 8 x 1.28 = 10.24 sec. 10 : 4 x 1.28 = 5.12 sec. 11 : 2 x 1.28 = 2.56 sec. 8 r : ice-debugging mode detected 0 : ice-debugging mode 1 : free-run mode. 7 r/w : inverted data bus for access flash memory. 0 : inverted. 1 : non-inverted. 6 r: external rom detect. 0: firmware stored in external rom. 1: firmware stored in linear type flash memory array. 5:4 r/w: shadow rom space control 00 : 512 bytes, range: 7400h ~ 74ffh 01 : 1kbytes, range: 7400h ~ 75ffh 10 : 1.5kbytes, range: 7400h ~ 76ffh 11 : 2kbytes, range: 7400h ~ 77ffh 3:2 r : master/slave mode detect in true ide mode 00 : master of two drives 10 : slave of two drives 11 : one drive 1 r/w: pio/dma mode select 0: pio mode.
25 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 1: dma mode. 0 r/w: led output port 601dh : bit function description default reset value : 0000h 9:0 r/w : flash memory read address fa[24:15] latch in linear mode when data space 8000h ~ ffffh is read, the output of the flash memory read address latch will be used. the definitions for this register in series mode default reset value : 0000h 9 reserved. 8 bank select in capacity extension mode 0 : bank0 selected. 1 : bank1 selected. 7:5 r/w: fce select for series mode 000: fce0 001: fce2 010: fce4 011: fce6 100: fce1 101: fce3 110: fce5 111: fce7 4 r/w: command latch enable (fa19/cle) 0 : disable 1 : enable 3 r/w: address latch enable (fa18/ale) 0 : disable 1 : enable 2:0 reserved port 601eh : bit function description flash memory control register default reset value : 08ah 7 r/w: flash memory deep power down control 0 in linear mode or write protect in series mode 0 : enable 1 : disable 6 r : ready / busy status
26 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 0 : busy 1 : ready port 601eh : bit function description 5:4 r/w: flash memory type select 00 : reserved. 01 : 16m flash memory /bank 1 select in linear mode or capacity extension mode selected in series mode. 10 : reserved 11 : reserved 3 r/w: flash memory deep power down control 1 in linear mode or spare area enable in series mode. 0 : enable 1 : disable 2 r/w: ce# enable for series mode 0 : disable 1 : enable 1 r/w: series or linear mode select 0 : linear mode 1 : series mode 0 r/w: flash memory write pulse width control 0 : 1 system clock 1 : 2 system clock port 601fh : bit function description default reset value : 0000h 9 r/w : flash memory write address fa[24:15] latch in linear mode when data space 8000h ~ ffffh is write or program space 8000h ~ ffffh is read, the output of the flash memory write address latch will be used. the definitions for this register in series mode reserved. 8 bank select in capacity extension mode 0 : bank0 selected. 1 : bank1 selected. 7:0 reserved.
27 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 6. electrical specifications 6-1. dc characteristics 1 : ta = 0 o c to 70 o c, vcc = 5v 10% symbol parameter min max units conditions vcc power supply voltage 4.5 5.5 v vil1 input low voltage (ttl) 0.8 v vcc=5v vih1 input high voltage (ttl) 2.0 v vcc=5v vil2 input low voltage (cmos) 1.2 v vcc=5v vih2 input high voltage (cmos) 3.5 v vcc=5v vol output low voltage 0.4 v iol=8ma voh output high voltage 2.5 v ioh=-8ma icc1 supply current 1 40 ma f=25mhz, active mode, cl=0pf, vcc=5.5volt, temperature= 0 o c icc2 supply current 2 30 ma f = 25mhz, idle mode, cl = 0pf, vcc=5.5volt, temperature= 0 o c icc3 supply currect 3 12 ma f = 25mhz, standby mode, cl = 0pf, vcc=5.5volt, temperature= 0 o c icc4 supply current 4 1 ma f = 0mhz, sleep mode, cl = 0pf, vcc=5.5volt, temperature= 0 o c il input leakage 10 ua 0< vin < vcc cin input capacitance 14 pf vin=0v cout output capacitance 16 pf vout=0v note : during transitions, inputs may undershoot to -2.0v for periods less than 20ns and overshoot to vcc + 2.0v for periods less than 20ns.
28 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 6-2. dc characteristics 2 : ta = 0 o c to 70 o c, vcc = 3.3v 5% symbol parameter min max units conditions vcc power supply voltage 3.1 3.5 v vil1 input low voltage(ttl) 0.8 v vcc=3.3v vih1 input high voltage(ttl) 2.0 v vcc=3.3v vil2 input low voltage(cmos) 0.9 v vcc=3.3v vih2 input high voltage(cmos) 2.7 v vcc=3.3v vol output low voltage 0.4 v iol=4ma voh output high voltage 2.2 v ioh=-4ma icc1 supply current 1 20 ma f=16mhz, active mode, cl=0pf, vcc=3.5volt, temperature= 0 o c icc2 supply current 2 15 ma f = 16mhz, idle mode, cl = 0pf, cc=3.5volt, temperature= 0 o c icc3 supply currect 3 5 ma f = 16mhz, standby mode, cl = 0pf, vcc=3.5volt, temperature= 0 o c icc4 supply current 4 0.5 ma f = 0mhz, sleep mode, cl = 0pf, vcc=3.5volt, temperature= 0 o c il input leakage 10 ua 0< vin < vcc cin input capacitance 14 pf vin=0v cout output capacitance 16 pf vout=0v note : during transitions, inputs may undershoot to -2.0v for periods less than 20ns and overshoot to vcc + 2.0v for periods less than 20ns.
29 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 6-3. ac characteristics condition : ta=0 o c to 70 o c, vcc = 5v 10% or vcc = 3.3v 5% (1). dsp interface timing : vcc = 5v 10% symbol description min. typ. max. units tw in ice mode, wr# pulse duration when the data are 4tc accessed by external dsp. trd in ice mode, rd# to output delay when the data are 34 ns accessed by external dsp. tcs chip select access cycle 1.5tc 4.5tc ns taa address access cycle 1.5tc 4.5tc ns trds data setup time before rd# high 12 ns tdh data hold time after rd# high 0 ns vcc = 3.3v 5% symbol description min. typ. max. units tw in ice mode, wr# pulse duration when the data are 4tc accessed by external dsp. trd in ice mode, rd# to output delay when the data are 34 ns accessed by external dsp. tcs chip select access cycle 1.5tc 4.5tc ns taa address access cycle 1.5tc 4.5tc ns trds data setup time before rd# high ns tdh data hold time after rd# high ns
30 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 wr# dce# a[15:0] tdh trds tcs ta a tw rd# d[15:0] a[15:0] d[15:0] dce#/pce# rd# dce# a[15:0] tr d d[15:0]
31 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 (2). power reset timing vcc = 5v 10% or vcc = 3.3v 5% symbol description min. typ. max. units tw(rst) reset low pulse width 3tc ns (3). clock timing vcc = 5v 10% symbol description min. typ. max. units tc(c) clock cycle time 40 ns tlpd(c) clock low pulse duration(tc=40ns) 16 24 ns thpd(c) clock high pulse duration(tc=40ns) 16 24 ns vcc = 3.3v 5% symbol description min. typ. max. units tc(c) clock cycle time 62.5 ns tlpd(c) clock low pulse duration(tc=62.5ns) 25 37.5 ns thpd(c) clock high pulse duration(tc=62.5ns) 25 37.5 ns tw(rst) clk in pwr rst# tc tlpd thp
32 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 (4). interrupt timing vcc = 5v 10% symbol description min. typ. max. units tw int1# low pulse duration 1.5tc ns tf int1# fall time 10 ns vcc = 3.3v 5% symbol description min. typ. max. units tw int1# low pulse duration 1.5tc ns tf int1# fall time ns (5). hold# timing vcc = 5v 10% or vcc = 3.3v 5% symbol description min. typ. max. units td(al-h) hlda# low to address tri-state 0 ns td(hh-ha) hold# high to hlda# high 0 0.5tc 0.5tc+10 ns ten(ah-a) address driven after hlda# high 0.5tc-10 0.5tc tc ns hold# int1 td(al-h) td(hh-ha) tf hlda# a[15:0] tw ten(ah-a)
33 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 (6). pcmcia bus timing 1: common memory and attribute memory access timing vcc = 5v 10% symbol parameter min (ns) max (ns) t1 read cycle time 60 t2 chip enable setup time before output enable 0 t3 output data enable time from hoe# 31 t4 chip disable hold time following output disable 1.5 t5 output data disable time following hoe# 10.5 t6 write cycle time 60 t7 chip enable setup time before hwe# 0 t8 write pulse width of hwe# 40 t9 chip disable hold time following write disable 2 t10 data setup time before hwe# 0 t11 data hold time following hwe# 2.5 vcc = 3.3v5% symbol parameter min (ns) max (ns) t1 read cycle time 90 t2 chip enable setup time before output enable 0 t3 output data enable time from hoe# 47 t4 chip disable hold time following output disable 3 t5 output data disable time following hoe# 17 t6 write cycle time 90 t7 chip enable setup time before hwe# 0 t8 write pulse width of hwe# 60 t9 chip disable hold time following write disable 2.5 t10 data setup time before hwe# 0 t11 data hold time following hwe# 3
34 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 ce[2:1]# hoe# ha[10:0] reg# common memory and attribute memory read timing t3 t2 hd[15:0] t1 t5 t4 ce[2:1]# hwe# ha[10:0] reg# common memory and attribute memory writetiming t7 hd[15:0] t8 t6 t10 t11 t9
35 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 (7). pcmcia bus timing 2: i/o mode access timing vcc = 5v 10% symbol parameter min (ns) max (ns) t1 address hold time following ior# 2 t2 reg# setup time before ior# 0 t3 reg# hold time following ior# 0 t4 ce# setup time before ior# 0 t5 ior# pulse width 60 t6 ce# hold time following ior# 2 t7 address setup time before ior# 0 t8 inpack delay from ior# falling edge 10 t9 inpack delay from ior# rising edge 10.5 t10 iois16 falling delay after address changed 14 t11 data delay after ior# falling 32 t12 iois16 rising delay after address changed 12.5 t13 data hold time following ior# 20 t14 address hold time following iow# 3 t15 reg# setup time before iow# 0 t16 reg# hold time following iow# 0 t17 ce# setup time before iow# 0 t18 iow# pulse with 60 t19 ce# hold time following iow# 2 t20 address setup time before iow# 0 t21 iois16 rising delay after address changed 10.5 t22 iois16 falling delay after address changed 14 t23 data setup time before iow# 0 t24 data hold time following iow# 2.5
36 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 vcc = 3.3v 5% symbol parameter min (ns) max (ns) t1 address hold time following ior# 2 t2 reg# setup time before ior# 0 t3 reg# hold time following ior# 0 t4 ce# setup time before ior# 0 t5 ior# pulse width 90 t6 ce# hold time following ior# 2 t7 address setup time before ior# 0 t8 inpack delay from ior# falling edge 18 t9 inpack delay from ior# rising edge 18 t10 iois16 falling delay after address changed 23.5 t11 data delay after ior# falling 47 t12 iois16 rising delay after address changed 20 t13 data hold time following ior# 31 t14 address hold time following iow# 4 t15 reg# setup time before iow# 0 t16 reg# hold time following iow# 0 t17 ce# setup time before iow# 0 t18 iow# pulse with 90 t19 ce# hold time following iow# 2.5 t20 address setup time before iow# 0 t21 iois16 rising delay after address changed 20 t22 iois16 falling delay after address changed 23.5 t23 data setup time before iow# 0 t24 data hold time following iow# 3
37 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 ce[2:1]# inpack# ha[10:0] id read timing iois16# reg# ior# t7 t2 hd[15:0] t1 t4 t8 t5 t9 t12 t13 t10 t11 t3 t6 i/o write timing ce[2:1]# ha[10:0] iois16# reg# iow# t20 t15 hd[15:0] t14 t17 t18 t21 t24 t22 t23 t16 t19
38 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 (8). flash memory interface timing vcc = 5v 10% symbol parameter min max units tw(a-ce) fce# fall time after dsp address decode when write 5.5 15 ns twas fce# setup time before wrflash# falling edge 10 29.5 ns tw(wrflash) wrflash# low pulse duration 1tc * ns tr(a-ce) fce# fall time after dsp address decode when read 5.5 15 ns tr(rd-oe) rdflash# fall time after rd# falling edge 4.5 11.5 ns vcc = 3.3v 5% symbol parameter min max units tw(a-ce) fce# fall time after dsp address decode when write 8 24.5 ns twas fce# setup time before wrflash# falling edge 14.5 49 ns tw(wrflash) wrflash# low pulse duration 1tc * ns tr(a-ce) fce# fall time after dsp address decode when read 8 24.5 ns tr(rd-oe) rdflash# fall time after rd# falling edge 6.5 20 ns [ * note]: theses timing are only for 1-system clock of flash memory write pulse is employed (601e[0]=0). if 2-system clock of pulse width is selected (601e[0]=1), the minimum time of tw(wrflash) is 2tc. wrflash# a[15:0] flash memory write timing fce[7:0] wr# tw(a-ce) tw a s tw(wrflash) rdflash# a[15:0] flash memory read timing fce[7:0] rd# tr(a-ce) tr a s
39 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 6-4. latchup characteristics min. max. input voltage with respect to gnd on all vcc pins -2.0v 12.0v input voltage with respect to gnd on all i/o pins -2.0v vcc+2.0v current -100ma +100ma includes all pins expect gnd. test conditions:vcc=5.0v, one pin at a time.
40 MX9691L p/n:pm0546 rev. 1.1, jul. 02, 1999 revision history revision destription page date 1.1 modify package type p1 jul/02/1999
MX9691L 41 m acronix i nternational c o., l td. headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-348-8385 fax:+65-348-8096 taipei office: tel:+886-2-509-3300 fax:+886-2-509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice.

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